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dpa422-426 dpa-switch family www.powerint.com december 2007 highly integrated dc-dc converter ics for power over ethernet & telecom applications ? output power table 36-75 vdc input range (forward) 2 total device dissipation 3 product 4 0.5 w 1 w 2.5 w 4 w 6 w max power output 1 dpa422 7 7.5 w 10 w - - - 10 w dpa423 12 w 16 w - - - 18 w dpa424 16 w 23 w 35 w - - 35 w dpa425 23 w 32 w 50 w 62 w - 70 w dpa426 5 25 w 35 w 55 w 70 w 83 w 100 w 36-75 vdc input range (flyback) 2 total device dissipation 3 product 4 0.5 w 0.75 w 1 w 1.5 w max power output 1 dpa422 6.5 w 9.0 w - - 9.0 w dpa423 9 w 13 w - - 13 w dpa424 10 w 14.5 w 18 w 24 w 26 w dpa425 - 6 - 6 - 6 25.5 w 52 w table 1. output power table. notes: 1. maximum output power is limited by device internal current limit. 2. see applications considerations section for complete description of assumptions and for output powers with other input voltage ranges. 3. for device dissipation of 1.5 w or below, use p or g packages. device dissipation above 1.5 w is possible with r package. 4. packages: p: dip-8, g: smd-8, r: to-263-7c. for lead-free package options, see part ordering information. 5. available in r package only. 6. due to higher switching losses, the dpa425 may not deliver additional power compared to a smaller device. 7. available in p and g package only. product highlights highly integrated solution eliminates up to 50 external componentsCsaves space, cost integrates 220 v high frequency mosfet, pwm control lower cost plastic dip surface mount (g package) and through-hole (p package) options for designs 35 w thermally ef? cient to-263-7c (r package) option for high power a pplications superior performance and flexibility eliminates all external current sensing circuitry built-in auto-restart for output overload/open loop protection pin selectable 300/400 khz ? xed frequency wide input (line) voltage range: 16-75 vdc externally programmable current limit source connected tab reduces emi line under-voltage (uv) detection: meets etsi standards line overvoltage (ov) shutdown protection uv/ov limits gate drive voltage for synchronous recti? cation fully integrated soft-start for minimum stress/overshoot supports forward or ? yback topology cycle skipping: regulation to zero load without pre-load hysteretic thermal shutdown for automatic fault recovery rohs compliant p and g package options ecosmart ? C energy ef? cient extremely low consumption at no load cycle skipping at light load for high standby ef? ciency applications poe applications, voip phones, wlan, security cameras telco central of? ce equipment: xdsl, isdn, pabx distributed power architectures (24 v/48 v bus) industrial controls description the dpa-switch ic family is a highly integrated solution for dc-dc conversion applications with 16-75 vdc input. dpa-switch uses the same proven topology as topswitch ? , cost effectively integrating a power mosfet, pwm control, fault protection and other control circuitry onto a single cmos chip. high performance features are enabled with three user con? gurable pins. hysteretic thermal shutdown is also provided. in addition, all critical parameters (i.e. current limit, frequency, pwm gain) have tight temperature and absolute tolerance, to simplify design and reduce system cost. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 1. typical forward converter application. pi-2770-032002 d s c dpa-switch v in v o f x l control sense circuit reset/ clamp circuit
rev. s 12/07 2 dpa422-426 www.powerint.com section list functional block diagram ............................................................................................................................ ........... 3 pin functional description ............................................................................................................................ .......... 3 dpa-switch family functional description ............................................................................................................ 4 control (c) pin operation .................................................................................................... ................................ 4 oscillator and switching frequency .......................................................................................................................... 5 pulse width modulator & maximum duty cycle ................................................................................... ..................... 5 minimum duty cycle and cycle skipping ........................................................................................ ......................... 6 error ampli? er .............................................................................................................. ............................................ 6 on-chip current limit with external programmability .......................................................................... ...................... 6 line under-voltage detection (uv) ............................................................................................................................ 6 line overvoltage shutdown (ov) ............................................................................................... ............................... 6 line feed-forward with dc max reduction ................................................................................................................ 6 remote on/off ................................................................................................................ ...................................... 7 synchronization ............................................................................................................................... ......................... 7 soft-start ................................................................................................................... .............................................. 8 shutdown/auto-restart ........................................................................................................ ................................... 8 hysteretic over-temperature protection ....................................................................................... ............................ 8 bandgap reference ............................................................................................................ ..................................... 8 high-voltage bias current source ............................................................................................. ............................... 8 using feature pins ............................................................................................................................. ........................ 8 frequency (f) pin operation .................................................................................................. .............................. 8 line-sense (l) pin operation ................................................................................................. ................................ 9 external current limit (x) pin operation ..................................................................................... .................... 9 typical uses of frequency (f) pin ...................................................................................................................... 11 typical uses of line-sense (l) and external current limit (x) pins ....................................................... 11 application examples ............................................................................................................................. ................. 14 key application considerations .............................................................................................................................. 1 6 dpa-switch design considerations ............................................................................................. ........................... 16 dpa-switch layout considerations ............................................................................................. ........................... 18 quick design checklist ....................................................................................................... ................................... 19 design tools ................................................................................................................. ......................................... 20 product speci? cations and test conditions .......................................................................................................... 21 typical performance characteristics .................................................................................................................. 27 part ordering information ............................................................................................................................. .......... 30 package outlines ............................................................................................................................ ........................ 31
rev. s 12/07 3 dpa422-426 www.powerint.com figure 2. functional block diagram. pin functional description drain (d) pin: high voltage power mosfet drain output. the internal startup bias current is drawn from this pin through a switched high- voltage current source. internal current limit sense point for drain current. control (c) pin: error ampli? er and feedback current input pin for duty cycle control. internal shunt regulator connection to provide internal bias current during normal operation. it is also used as the connection point for the supply bypass and auto-restart/ compensation capacitor. line-sense (l) pin: input pin for overvoltage (ov), under-voltage (uv) lock out, line feed-forward with the maximum duty cycle (dc max ) reduction, remote on/off and synchronization. a connection to source pin disables all functions on this pin. external current limit (x) pin: input pin for external current limit adjustment and remote on/off. a connection to source pin disables all functions on this pin. frequency (f) pin: input pin for selecting switching frequency: 400 khz if connected to source pin and 300 khz if connected to control pin. source (s) pin: output mosfet source connection for the power return. primary side control circuit common and reference point. pi-2760-070501 shutdown/ auto-restart pwm comparator clock saw 300/400 khz controlled turn-on gate driver current limit comparator internal uv comparator internal supply 5.8 v 4.8 v source (s) s r q d max stop soft- start - + control (c) line-sense (l) external current limit (x) frequency (f) - + 5.8 v 1 v i fb r e z c v c + - leading edge blanking 8 1 hysteretic thermal shutdown shunt regulator/ error amplifier + - drain (d) on/off soft start dc max v bg dc max v bg + v t 0 ov/uv v i (limit) current limit adjust line sense soft start cycle skipping stop logic oscillator tab internally connected to source pin (see layout considerations) r package (to-263-7c) 1234 5 7 clxs f d f s l x s d s c 4 2 3 1 p package (dip-8) g package (smd-8) 5 7 8 6 pi-4030-110507 figure 2. pin con? guration (top view).
rev. s 12/07 4 dpa422-426 www.powerint.com figure 4. relationship of duty cycle to control pin current. dpa-switch family functional description dpa-switch is an integrated switched mode power supply chip that converts a current at the control input to a duty cycle at the open drain output of a high voltage power mosfet. during normal operation the duty cycle of the power mosfet decreases linearly with increasing control pin current as shown in figure 4. a patented high-voltage cmos technology allows both the high-voltage power mosfet and all the low voltage control circuitry to be cost effectively integrated onto a single monolithic chip. in addition to the standard topswitch features, such as the high-voltage start-up, the cycle-by-cycle current limiting, loop compensation circuitry, auto-restart and thermal shutdown, dpa-switch also offers many advanced features that reduce system cost and increase power supply performance and design ? exibility. following is a summary of the advanced features: a fully integrated 5 ms soft-start limits peak currents and voltages during start-up and reduces or eliminates output overshoot in most applications. a 75% maximum duty cycle (dc max ) together with the line feed-forward with dc max reduction feature makes dpa-switch well suited for both ? yback and forward topologies. high switching frequency (400 khz/300 khz, pin selectable) allows the use of smaller size transformers and offers high bandwidth for power supply control loop. cycle skipping operation at light load minimizes standby power consumption (typically <10 ma input current). line under-voltage ensures glitch free operations at both power-up and power-down and is tightly toleranced over process and temperature to meet system level requirements common in dc to dc converters (e.g. etsi). line overvoltage protects dpa-switch against excessive input voltage and line surge. external current limit adjustment allows the setting of the current limit externally to a lower level near the operating peak current and, if desired, further adjusts the level gradu- ally as line voltage rises. this makes possible an ideal implementation of overload power limiting. synchronization function allows the synchronization of dpa-switch operation to an external lower frequency. remote on/off feature permits dpa-switch based power supplies to be easily switched on/off using logic signals. maximum input current consumption is 2 ma in remote off. hysteretic over-temperature shutdown provides automatic recovery from thermal fault. tight absolute tolerances and small temperature variations on switching frequency, current limit, and undervoltage lock out threshold (uv). three pins, line-sense (l), external current limit (x) and frequency (f), are used to implement all the pin - controllable features. a resistor from the line-sense pin to dc input bus implements line uv, line ov and line feed-forward with dc max reduction. a resistor from the external current limit pin to the source pin sets current limit externally. in 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. addition, remote on/off may be implemented through either the line-sense pin or the external current limit pin depending on the polarity of the logic signal available as well as other system speci? c considerations. shorting both the line- sense and the external current limit pins to the source pin disables line ov, line uv, line feed-forward with dc max reduction, external current limit, remote on/off and synchronization. the frequency pin sets the switching frequency to 400 khz if connected to the source pin, or 300 khz if connected to the control pin. this pin should not be left open. please refer to using feature pins section for detailed information regarding the proper use of those pins. control (c) pin operation the control pin is a low impedance node that is capable of receiving a combined supply and feedback current. during normal operation, a shunt regulator is used to separate the feedback signal from the supply current. control pin voltage v c is the supply voltage for the control circuitry including the mosfet gate driver. an external bypass capacitor closely connected between the control and source pins is required to supply the instantaneous gate drive current. the total amount of capacitance connected to this pin also sets the auto-restart timing as well as control loop compensation. when the dc input voltage is applied to the drain pin during start-up, the mosfet is initially off, and the control pin capacitor is charged through the switched high voltage current source connected internally between the drain and control pins. when the control pin voltage v c reaches approximately 5.8 v, the control circuitry is activated and the soft-start begins. the soft-start circuit gradually increases the duty cycle of the mosfet from zero to the maximum value over approximately 5 ms. the high voltage current source is turned off at the end of the soft-start. if no external feedback/ supply current is fed into the control pin by the end of the soft-start, the control pin will start discharging in response to the supply current drawn by the control circuitry and the gate current of the switching mosfet driver. if the power supply is designed properly, and no fault condition such as open loop or pi-2761-112102 duty cycle (%) i c (ma) i l = 115 a i l < i l(dc) i c (skip) slope = pwm gain i cd1 i b auto-restart 75 4 42
rev. s 12/07 5 dpa422-426 www.powerint.com overloaded output exists, the feedback loop will close, providing external control pin current, before the control pin voltage has had a chance to discharge to the lower threshold voltage of approximately 4.8 v (internal supply undervoltage lockout threshold). when the externally fed current charges the control pin to the shunt regulator voltage of 5.8 v, current in excess of the consumption of the chip is shunted to source through resistor r e as shown in figure 2. this current ? owing through r e controls the duty cycle of the power mosfet to provide closed loop regulation. the shunt regulator has a ? nite low output impedance z c that sets the gain of the error ampli? er when used in a primary feedback con? guration. the dynamic impedance z c of the control pin together with the external control pin capacitance sets the dominant pole for the control loop. when a fault condition such as an open loop or overloaded output prevents the ? ow of an external current into the control pin, the capacitor on the control pin discharges towards 4.8 v. at 4.8 v auto-restart is activated which turns the output mosfet off and puts the control circuitry in a low current standby mode. the high-voltage current source turns on and charges the external capacitance again. a hysteretic internal supply under-voltage comparator keeps v c within a window of typically 4.8 v to 5.8 v by turning the high-voltage current source on and off as shown in figure 5. the auto- restart circuit has a divide-by-8 counter that prevents the output mosfet from turning on again until eight discharge/charge cycles have elapsed. this is accomplished by enabling the output mosfet only when the divide-by-8 counter reaches full count (s7). the counter effectively limits dpa-switch power dissipation as well as the maximum power delivered to the power supply output by reducing the auto-restart duty cycle to typically 4%. auto-restart mode continues until output voltage regulation is again achieved through closure of the feedback loop. oscillator and switching frequency the internal oscillator linearly charges and discharges an internal capacitance between two voltage levels to create a sawtooth waveform for the pulse width modulator. the oscillator sets both the pulse width modulator latch and the current limit latch at the beginning of each cycle. the nominal switching frequency of 400 khz was chosen to minimize the transformer size and to allow faster power supply loop response. the frequency pin, when shorted to the control pin, lowers the switching frequency to 300 khz, which may be preferable in some applications such as those employing secondary synchronous recti? cation. otherwise, the frequency pin should be connected to the source pin for the default 400 khz. pulse width modulator and maximum duty cycle the pulse width modulator implements voltage mode control by driving the output mosfet with a duty cycle inversely proportional to the current into the control pin that is in excess of the internal supply current of the chip (see figure 4). the excess current is the feedback error signal that appears across r e (see figure 2). this signal is ? ltered by an rc network with a typical corner frequency of 30 khz to reduce the effect of switching noise in the chip supply current generated by the mosfet gate driver. the ? ltered error signal is compared with the internal oscillator sawtooth waveform to generate the duty cycle waveform. as the control current increases, the duty cycle decreases. a clock signal from the oscillator sets a latch that turns on the output mosfet. the pulse width modulator resets the latch, turning off the output mosfet. note that a minimum current must be driven into the control pin before the duty cycle begins to change. pi-3867-050602 s1 s2 s6 s7 s1 s2 s6 s7 s0 s1 s7 s0 s0 5.8 v 4.8 v s7 0 v 0 v 0 v v line v c v drain v out note: s0 through s7 are the output states of the auto-restart counter 2 1 2 3 4 0 v ~ ~ ~ ~ ~ ~ ~ ~ s6 s7 ~ ~ ~ ~ ~ ~ v uv ~ ~ ~ ~ ~ ~ ~ ~ s2 ~ ~ figure 5. typical waveforms for (1) power up, (2) normal operation, (3) auto-restart and (4) power down.
rev. s 12/07 6 dpa422-426 www.powerint.com the maximum duty cycle, dc max is set at a default maximum value of 75% (typical). however, by connecting the line-sense to the dc input bus through a resistor with appropriate value, the maximum duty cycle can be made to decrease from 75% to 33% (typical) as shown in figure 7 when input line voltage increases (see line feed-forward with dc max reduction). minimum duty cycle and cycle skipping to maintain power supply output regulation, the pulse width modulator reduces duty cycle as the load at the power supply output decreases. this reduction in duty cycle is proportional to the current ? owing into the control pin. as the control pin current increases, the duty cycle reduces linearly towards a minimum value speci? ed as minimum duty cycle, dc min . after reaching dc min , if control pin current is increased further by approximately 2 ma, the pulse width modulator will force the duty cycle from dc min to zero in a discrete step (refer to figure 4). this feature allows a power supply to operate in a cycle skipping mode when the load consumes less power than the dpa-switch delivers at minimum duty cycle, dc min . no additional control is needed for the transition between normal operation and cycle skipping. as the load increases or decreases, the power supply automatically switches between normal and cycle skipping mode as necessary. cycle skipping may be avoided, if so desired, by connecting a minimum load at the power supply output such that the duty cycle remains at a level higher than dc min at all times. error ampli? er the shunt regulator can also perform the function of an error ampli? er in primary side feedback applications. the shunt regulator voltage is accurately derived from a temperature- compensated bandgap reference. the gain of the error ampli? er is set by the control pin dynamic impedance. the control pin clamps external circuit signals to the v c voltage level. the control pin current in excess of the supply current is separated by the shunt regulator and ? ows through r e as a voltage error signal. on-chip current limit with external programmability the cycle-by-cycle peak drain current limit circuit uses the output mosfet on-resistance as a sense resistor. a current limit comparator compares the output mosfet on-state drain to source voltage, v ds(on) with a threshold voltage. at the current limit, v ds(on) exceeds the threshold voltage and the mosfet is turned off until the start of the next clock cycle. the current limit comparator threshold voltage is temperature compensated to minimize the variation of the current limit due to temperature related changes in r ds(on) of the output mosfet. the default current limit of dpa-switch is preset internally. however, with a resistor connected between external current limit pin and source pin, the current limit can be programmed externally to a lower level between 25% and 100% of the default current limit. please refer to the graphs in the typical performance characteristics section for the selection of the resistor value. by setting current limit low, a larger dpa-switch than necessary for the power required can be used to take advantage of the lower r ds(on) for higher ef? ciency/smaller heat sinking requirements. with a second resistor connected between the external current limit pin and the dc input bus, the current limit is reduced with increasing line voltage, allowing a true power limiting operation against line variation to be implemented in a ? yback con? guration. the leading edge blanking circuit inhibits the current limit comparator for a short time after the output mosfet is turned on. the leading edge blanking time has been set so that, if a power supply is designed properly, current spikes caused by primary-side capacitance and secondary-side recti? er reverse recovery time should not cause premature termination of the switching pulse. the current limit after the leading edge blanking time is as shown in figure 31. to avoid triggering the current limit in normal operation, the drain current waveform should stay within the envelope shown. line under-voltage detection (uv) at power up , uv keeps dpa-switch off until the input line voltage reaches the under voltage upper threshold. at power down, uv holds dpa-switch on until the input voltage falls below the under voltage lower threshold. a single resistor connected from the line-sense pin to the dc input bus sets uv upper and lower thresholds. to avoid false triggering by noise, a hysteresis is implemented which sets the uv lower threshold typically at 94% of the uv upper threshold. if the uv lower threshold is reached during operation without the power supply losing regulation and the condition stays longer than 10 s (typical), the device will turn off and stay off until the uv upper threshold has been reached again. then, a soft-start will be initiated the next time control pin voltage reaches 5.8.v. if the power supply loses regulation before reaching the uv lower threshold, the device will enter auto-restart. at the end of each auto-restart cycle (s7), the uv comparator is enabled. if the uv upper threshold is not exceeded, the mosfet will be disabled during the next cycle (see figure 5). the uv feature can be disabled independent of ov feature. line overvoltage shutdown (ov) the same resistor used for uv also sets an overvoltage threshold which, once exceeded, will force the dpa-switch output into the off-state within one switching cycle. the ratio of ov and uv thresholds is preset at 2.7 as can be seen in figure 7. when the mosfet is off, the input voltage surge capability is increased to the voltage rating of the mosfet (220 v), due to the absence of the re? ected voltage and leakage spikes on the drain. a small amount of hysteresis is provided on the ov threshold to prevent noise triggering. the ov feature can be disabled independent of the uv feature as shown in figure 13. line feed-forward with dc max reduction the same resistor used for uv and ov also implements line voltage feed-forward that minimizes output line ripple and reduces power supply output sensitivity to line transients. this feed-forward operation is illustrated in figure 4 by the different values of i l . note that for the same control pin current, higher line voltage results in smaller operating duty cycle. as an added feature, the maximum duty cycle dc max is also reduced from 75% (typical) at a voltage slightly higher than the uv threshold to 33% (typical) at the ov threshold
rev. s 12/07 7 dpa422-426 www.powerint.com figure 6. synchronization timing diagram. (see figures 4, 7). limiting dc max at higher line voltages helps prevent transformer saturation due to large load transients in forward converter applications. dc max of 33% at the ov threshold was chosen to ensure that the power capability of the dpa-switch is not restricted by this feature under normal operation. remote on/off remote on/off control describes operation where the ic is turned on or off for long periods as opposed to the cycle-by- cycle on/off control, which is described in the synchronization section below. dpa-switch can be turned on or off by controlling the current into the line-sense pin or out from the external current limit pin (see figure 7). this allows easy implementation of remote on/off control of dpa-switch in several different ways. a transistor or an optocoupler output connected between the external current limit pin and the source pin implements this function with active-on (figures 17, 19 and 21) while a transistor or an optocoupler output connected between the line-sense pin and the control pin implements the function with active-off (figures 18, 20 and 22). when a signal is received at the line-sense pin or the external current limit pin to disable the output through any of the pin functions such as ov, uv and remote on/off, dpa-switch always completes its current switching cycle before the output is forced off. the internal oscillator is stopped at the end of the current cycle and stays there as long as the disable signal exists. when the signal at the above pins changes state from disable to enable, the internal oscillator starts the next switching cycle. the remote on/off feature can be used as a standby or power switch to turn off the dpa-switch and keep it in a very low power consumption state for inde? nitely long periods. if the dpa-switch is held in remote-off state for longer than 10 s (typical), the control pin goes into the hysteretic mode of operation. in this mode, the control pin goes through alternate charge and discharge cycles between 4.8 v and 5.8 v (see control pin operation section above) and the ic runs entirely off the high voltage dc input, but with very low power consumption (30 mw typical at 48 v with line-sense and external current limit pins open). when the dpa-switch is remotely turned on after entering this mode, it will initiate a normal start-up sequence with soft-start the next time the control pin reaches 5.8 v. in the worst case, the delay from remote on to start-up can be equal to the full discharge/charge cycle time of the control pin, which is approximately 36 ms for a 22 f control pin capacitor. this reduced- consumption remote-off mode can eliminate expensive and unreliable in-line mechanical switches. it also allows for microprocessor-controlled turn-on and turn-off sequences that may be required in certain applications. synchronization in addition to sensing incoming current for ov, uv and remote on/off, the line-sense pin also monitors its pin voltage through a 1 v threshold comparator. a pin voltage below 1 v turns on dpa-switch. when the voltage at line-sense pin rises beyond 1 v to disable the output, dpa-switch completes its current switching cycle before the output is forced off (similar to remote on/off operation). the internal oscillator is stopped at the end of the current cycle awaiting the line-sense pin voltage to go low to start the next cycle. this allows the use of the 1 v threshold to synchronize dpa-switch to an external signal with a frequency lower than its internal switching frequency. a transistor or an optocoupler output connected between the line-sense pin and the source pin implements this function (see figure 24). please refer to figure 6 for the timing waveforms of synchronization operation. pi-2762-070501 oscillator (saw) d max 2 v 0 v v l t on f sync 128 khz ; t off 7.7 s; 120 ns t on 2250 ns for f osc = 400 khz 3080 ns for f osc = 300 khz t off on off sync time
rev. s 12/07 8 dpa422-426 www.powerint.com table 2. typical line-sense and external current limit pin con? gurations. in order to be recognized as a synchronization pulse, the line-sense pin needs to stay low (on-time) for at least 120 ns but no more than 2250 ns for 400 khz (or 3080 ns for 300 khz) internal switching frequency. in addition, the off-time must be kept below 7.7 s, which is a limitation set by the lowest synchronization frequency of 128 khz allowed by the chip. the effective dc max for synchronization operation can be calculated as 0.75 f sync /f osc . an off-time longer than 7.7 s may force the control pin to go into the hysteretic mode and initiate a soft-start cycle at next turn-on. soft-start two on-chip soft-start functions are activated at start-up with a duration of 5 ms (typical). maximum duty cycle starts from 0% and linearly increases to the default maximum of 75% at the end of the 5 ms duration and the current limit starts from about 85% and linearly increases to 100% at the end of the 5 ms duration. in addition to start-up, soft-start is also activated at each restart attempt during auto-restart and when restarting after being in hysteretic regulation of control pin voltage (v c ), due to remote off or thermal shutdown conditions. this effectively minimizes current and voltage stresses on the output mosfet, the clamp circuit and the output recti? er during start- up. this feature also helps minimize output overshoot and prevents saturation of the transformer during start-up. shutdown/auto-restart to minimize dpa-switch power dissipation under fault conditions, the shutdown/auto-restart circuit turns the power supply on and off at an auto-restart duty cycle of typically 4% if an out of regulation condition persists. loss of regulation interrupts the external current into the control pin. v c regulation changes from shunt mode to the hysteretic auto- restart mode as described in control pin operation section. when the fault condition is removed, the power supply output becomes regulated, v c regulation returns to shunt mode, and normal operation of the power supply resumes. hysteretic over-temperature protection over temperature protection is provided by a precision analog circuit that turns the output mosfet off when the junction temperature exceeds the thermal shutdown temperature (137 c typical). when the junction temperature cools to below the hysteretic temperature (110 c typical), normal operation resumes providing automatic recovery. v c is regulated in hysteretic mode and a 4.8 v to 5.8 v (typical) sawtooth waveform is present on the control pin while in thermal shutdown. bandgap reference all critical dpa-switch internal voltages are derived from a temperature-compensated bandgap reference. this reference is also used to generate a temperature-compensated current reference that is trimmed to accurately set the switching frequency, current limit, and the line ov/uv thresholds. dpa-switch has improved circuitry to maintain all of the above critical parameters within very tight absolute and temperature tolerances. high-voltage bias current source this current source biases dpa-switch from the drain pin and charges the control pin external capacitance during start-up or hysteretic operation. hysteretic operation occurs during auto-restart, remote off and over-temperature shutdown. in this mode of operation, the current source is switched on and off with an effective duty cycle of approximately 20%. this duty cycle is determined by the ratio of control pin charge (i c(ch) ) and discharge currents (i cd1 and i cd2 ). this current source is turned off during normal operation when the output mosfet is switching. the effect of the current source switching may be seen on the drain voltage waveform as small disturbances, which is normal. using feature pins frequency (f) pin operation the frequency pin is a digital input pin. shorting the frequency pin to source pin selects the nominal switching frequency of 400 khz (figure 9) which is suited for most applications. for other applications that may bene? t from lower switching frequency, a 300 khz switching frequency can be selected by shorting the frequency pin to the control pin (figure 10). this pin should not be left open. line-sense and external current limit pin table* figure number ? 11 12 13 14 15 16 17 18 19 20 21 22 23 24 three terminal operation ? undervoltage ?? ??? overvoltage ? ? ??? line feed-forward (dc max ) ? ??? overload power limiting ? external current limit ?? ??? ? remote on/off ?????? synchronization ? *this table is only a partial list of many line-sense and external current limit pin con? gurations that are possible.
rev. s 12/07 9 dpa422-426 www.powerint.com line-sense (l) pin operation when current is fed into the line-sense pin, it works as a voltage source of approximately 2.6 v up to a maximum current of +240 a (typical). at +240 a, this pin turns into a constant current sink. refer to figure 8. in addition, a comparator with a threshold of 1 v is connected at the pin and is used to detect when the pin is shorted to the source pin. there are a total of ? ve functions available through the use of the line-sense pin: ov, uv, line feed-forward with dc max reduction, remote on/off and synchronization. shorting the line-sense pin to the source pin disables all ? ve functions. the line-sense pin is typically used for line sensing by connecting a resistor from this pin to the positive input dc voltage bus to implement ov, uv and line feed-forward with dc max reduction over line voltage. in this mode, the value of the resistor determines the line ov/uv thresholds, and the dc max is reduced linearly with input dc high voltage starting from just above the uv threshold. this pin can also be used as the input pin for remote on/off and synchronization. an external transistor placed between the line-sense pin and the control pin realizes remote on/off via uv or ov threshold. synchronization is available by connecting an open drain external mosfet between the line-sense pin and the source pin to generate synchronization pulse. each time the mosfet turns on, the falling edge of the line-sense pin voltage initiates a new switching cycle. the lowest synchronization frequency guaranteed by dpa-switch is 128 khz. refer to table 2 for possible combinations of the functions with example circuits shown in figure 11 through figure 24. a description of speci? c functions in terms of the line-sense pin i/v characteristic is shown in figure 7 (right hand side). the horizontal axis represents line-sense pin current with positive polarity indicating currents ? owing into the pin. the meaning of the vertical axes varies with functions. for those that control the on/off states of the output such as uv, ov and remote on/off, the vertical axis represents the enable/ disable states of the output. uv triggers at i uv (+50 a typical with 4 a hysteresis) and ov triggers at i ov (+135 a typical with 4 a hysteresis). between the uv and ov thresholds, the output is enabled. for line feed-forward with dc max reduction, the vertical axis represents the magnitude of the dc max line feed-forward with dc max reduction lowers maximum duty cycle from 75% at i l(dc) (+55 a typical) to 33% at i ov (+135 a). external current limit (x) pin operation when current is drawn out of the external current limit pin, it works as a voltage source of approximately 1.3 v up to a maximum current of -230 a (typical). at -230 a, it turns into a constant current source (refer to figure 8). there are two functions available through the use of the external current limit pin: external current limit and remote on/off. shorting the external current limit pin and source pin disables both functions. in high ef? ciency applications, this pin can be used to reduce the current limit externally to a value close to the operating peak current, by connecting the pin to the source pin through a resistor. the pin can also be used as a remote on/off control input. table 2 shows several different ways of using this pin. see figure 7 for a description of the functions where the horizontal axis (left hand side) represents the external current limit pin current. the meaning of the vertical axes varies with function. for those that control the on/off states of the output such as remote on/off, the vertical axis represents the enable/ disable states of the output. for external current limit, the vertical axis represents the magnitude of the i limit . please see graphs in the typical performance characteristics section for the current limit programming range and the selection of the appropriate resistor value.
rev. s 12/07 10 dpa422-426 www.powerint.com figure 7. line-sense and external current limit pin characteristics. -250 -200 -150 -100 -50 50 100 150 200 250 0 0 pi-2778-080801 output mosfet switching (enabled) (disabled) (enabled) (disabled) i limit (default) current limit v bg -21.5 a -25.5 a v bg + v tp i uv(u) i rem(u) i ov(u) x pin voltage output mosfet switching maximum duty cycle l pin voltage dc max (75%) note: these figures provide idealized functional characteristics with typical performance values. please refer to the parametric table and typical performance characteristics sections of the data sheet for measured data. x pin current ( a) l pin current ( a) 131 a 135 a 47 a v bg + v t 1 v v bg 230 a 240 a control (c) (voltage sense) (positive current sense - under-voltage, overvoltage, on/off maximum duty cycle reduction) (negative current sense - on/off, current limit adjustment) pi-2765-061704 dpa-switch line-sense (l) external current limit (x) figure 8. line-sense (l), and external current limit (x) pin input simpli? ed schematic
rev. s 12/07 11 dpa422-426 www.powerint.com typical uses of frequency (f) pin typical uses of line-sense (l) and external current limit (x) pins figure 9. 400 khz frequency operation. pi-2654-071700 dc input voltage + - d s c control f xf pi-2766-070901 dc input voltage + - d s c control l cs d cl x s f d figure 11. three terminal operation (line-sense and external current limit features disabled. frequency pin can be tied to source or control pin). figure 13. line-sensing for under-voltage only (overvoltage disabled). pi-2852-121504 dc input voltage + - dl s c v uv = r ls x i uv + v l (i l = i uv ) for values shown v uv = 33.1 v r ls 15 v 464 k 1% 150 k 1% control figure 14. line-sensing for overvoltage only (under-voltage disabled). maximum duty cycle will be reduced at low line. pi-2853-091302 dc input voltage + - d s c control l r ls 1n4148 v ov = i ov x r ls + v l (i l = i ov ) for values shown v ov = 86.2 v 590 k 1% 30 k 1% figure 12. line-sensing for under-voltage, overvoltage and line feed-forward. pi-2767-091302 dc input voltage + - d s c control l r ls 619 k 1% v uv = i uv x r ls + v l (i l = i uv ) v ov = i ov x r ls + v l (i l = i ov ) for r ls = 619 k v uv = 33.3 v v ov = 86.0 v figure 10. 300 khz frequency operation. pi-2655-071700 dc input voltage + - d s c control f
rev. s 12/07 12 dpa422-426 www.powerint.com typical uses of line-sense (l) and external current limit (x) pins (cont.) figure 15. externally set current limit. figure 16. current limit reduction with line voltage. x pi-2836-011904 dc input voltage + - d s c r il for r il = 12 k i limit = 64% see figure 34 for other resistor values (r il ) for r il = 25 k i limit = 34% control x pi-2854-050602 dc input voltage + - d s c 363 k r ls 4.2 k r il 100% @ 36 vdc 64% @ 72 vdc i limit = i limit = control figure 17. active-on (fail safe) remote on/off. figure 18. active-off remote on/off. maximum duty cycle will be reduced. pi-2855-050602 dc input voltage + - d s c control l 47 k q r r mc 37.4 k q r can be an optocoupler output or can be replaced by a manual switch. on/off x pi-2625-040501 dc input voltage + - d s c on/off 47 k q r can be an optocoupler output or can be replaced by a manual switch. q r control figure 19. active-on remote on/off with externally set current limit. figure 20. active-off remote on/off with externally set current limit. x on/off 47 k pi-2856-072602 dc input voltage + - d s c r il q r for r il = 12 k i limit = 64% for r il = 25 k i limit = 34% q r can be an optocoupler output or can be replaced by a mosfet or manual switch. control pi-2857-050602 dc input voltage + - d s c control l 47 k q r r mc 37.4 k q r can be an optocoupler output or can be replaced by a manual switch. on/off x r il for r il = 12 k i limit = 64% for r il = 25 k i limit = 34%
rev. s 12/07 13 dpa422-426 www.powerint.com typical uses of line-sense (l) and external current limit (x) pins (cont.) pi-2858-072602 dc input voltage + - d s c control l 47 k 619 k 1% q r r ls on/off for r ls = 619 k v uv = 33.3 v v ov = 86.0 v q r can be an optocoupler output or can be replaced by a mosfet or manual switch. x on/off 47 k pi-2859-050602 dc input voltage + - d s c control l r il r ls q r 619 k 1% dc max @36 v = 75% dc max @72 v = 42% for r il = 12 k i limit = 64% q r can be an optocoupler output or can be replaced by a manual switch. figure 21. active-on remote on/off with line-sense and external current limit. figure 22. active-off remote on/off with line-sense. figure 23. line-sensing and externally set current limit. pi-3868-050602 dc input voltage + - d s c control l on/off 47 k q r can be an optocoupler output. q r for timing requirements, see figure 6. figure 24. synchronization. x pi-2837-011904 dc input voltage + - d s c control l r il r ls 12 k 619 k 1% for r ls = 619 k dc max @36 v = 75% dc max @72 v = 42% for r il = 12 k i limit = 64% see figure 34 for other resistor values (r il ) to select different i limit values v uv = 33.3 v v ov = 86.0 v
rev. s 12/07 14 dpa422-426 www.powerint.com figure 25. a high ef? ciency 30 w, 5 v, telecom input dc-dc converter. u1 dpa425r d1 bav 19ws d2 c5 220 nf vr1 smbj 150 c6 68 f 10 v c7 1 nf 1.5 kv r14 10 t1 r3 18.2 k 1% r1 619 k 1% r4 1.0 c10 100 f 10 v c11 100 f 10 v c12 1 f 10 v 36-75 vdc l1 1 h 2.5 a l2 c1, c2 & c3 1 f 100 v dl sxf c control control u2 pc357n1t pi-3472-061704 dpa-switch 5 v, 6 a rtn q2 si4888 dy c9* r5* *optional components r15 10 r16 10 k d4 bav19ws r17 10 q1 si4888 dy c4 4.7 f 20 v u2 d3 bav19ws u3 lm431aim3 r9 220 r11 10.0 k 1% r10 10.0 k 1% r12 5.1 r7 10 k c14 1 f c13 10 f 10 v c16 100 nf r6 150 v in + v in c17 3300 pf high ef? ciency 30 w forward converter the circuit shown in figure 25 is a typical implementation of a single output dc-dc converter using dpa-switch in a forward con? guration with synchronous recti? cation. this design delivers 30 w at 5 v, from a 36 vdc to 75 vdc input with a nominal ef? ciency at 48 vdc of 90% using the dpa425r. by taking advantage of many of the built-in features of the dpa-switch, the design is greatly simpli? ed compared to a discrete implementation. resistor r1 programs the input under- voltage and overvoltage thresholds to typically 33 v and 86 v respectively. this resistor also linearly reduces the maximum duty from the internal maximum of 75% at 36 v to 42% at 72 v to prevent core saturation during load transients at high input voltages. the dpa-switch internal thresholds are toleranced and characterized so the designer can guarantee the converter will begin operation at 36 v, necessary to meet etsi standards, without the cost of an external reference ic. the current limit is externally set by resistor r3 to just above the drain current level needed for maximum load regulation to limit the maximum overload power of the converter. the externally programmable current limit feature also allows a larger dpa-switch family member to be selected. using the x pin, the current limit can be adjusted to the same level. a large device reduces conduction losses and improves ef? ciency without requiring any other circuit changes. this has been used here to replace the dpa424r with a dpa425r. application examples the selectable 300/400 khz switching frequency is set to 300 khz by connecting the frequency (f) pin to control (c). drain voltage clamping is provided by vr1, which keeps the peak drain voltage within acceptable limits. transformer core reset is provided by the gate capacitance of q1 with r17 in series. optional reset capacitance c9 with r5 can be added if necessary to supplement the gate capacitance of q1. the output of the transformer is recti? ed using mosfets to provide synchronous recti? cation. the uv/ov function, together with the turns ratio of the transformer, de? nes the maximum mosfet gate voltage, allowing the very simple gate drive arrangement, without the need for drive windings or a drive ic. during primary on-time, capacitor c17 couples charge through resistor r15 to drive the gate of the forward mosfet, q2. capacitor c17 provides a dc isolated drive for q2, preventing gate overstress on q1 during power down. the time constant formed by r16 and c17 is selected to be much longer than one switching cycle. diode d4 resets the voltage on capacitor c17 before the next switching cycle. during the primary off-time, the diode d2 provides a conduction path for the energy in inductor l2 while q1 is still off. the transformer reset voltage on the secondary winding directly drives a positive voltage on the gate of catch mosfet, q1. mosfet q1 provides a low loss conduction path for a substantial portion of the primary off-time. an isolated auxiliary winding on l2, recti? ed and ? ltered by d1 and c4, provides the bias supply for the optocoupler transistor.
rev. s 12/07 15 dpa422-426 www.powerint.com d s c l f x control dpa-switch c4 22 f 10 v c3 0.1 f 50 v c10 0.33 f c11 0.1 f c8 1 f 50 v c9 1 f 10 v c7 330 f 6 v l1 1 h, 2a c6 330 f 6 v c5 330 f 6 v c1 1 f 100 v c2 47 pf 200 v vr1 smaj 150a r1 1 m 1% r3 8.66 k 1% r4 5.1 r9 20 k 1% r8 34 k 1% r7 1 k r5 100 r6 51 r2 619 k 1% 9, 10 1 2 3 6, 7 4 t1 5 u1 dpa423g u2 pc357 u3 cat431l, sot23 d3 bav19, sod323 d2 sl43 +v in 36 - 57 vdc j1-1 3.3 v, 2 a j2-1 -v in j1-2 rtn j2-2 pi-3806-061704 figure 26. a cost effective 6.6 w, 3.3 v flyback dc-dc converter. output regulation is achieved by using secondary side voltage reference, u3. the resistor divider formed by r10 and r11, together with the reference voltage, determines the output voltage. diode d3 and c13 form a soft-? nish network that, together with the internal duty cycle and current limit soft-start of the dpa-switch, prevent output overshoot at start-up. resistor r7 ensures that the soft-? nish capacitor is discharged quickly when the output falls out of regulation. control loop response is shaped by r6, c16, r12, c14, r9, r4 and c5, providing a wide bandwidth and good phase margin at gain crossover. since the pwm control in dpa-switch is voltage mode, no slope compensation is required for duty cycles above 50%. cost effective 6.6 w flyback converter the dpa-switch ? yback power supply provides a cost effective solution for high density poe and voip dc-dc applications. figure 26 shows a typical implementation of a single output ? yback converter using the dpa423g. for applications that require input to output isolation, this simple, low component count design delivers 6.6 w at 3.3 v from a 36 vdc to 57 vdc input with a nominal ef? ciency at 48 vdc of 80%. resistor r2 programs the input under-voltage and overvoltage thresholds to 33 v and 86 v respectively. resistors r1 and r3 program the internal device current limit. the addition of line sense resistor r1 reduces the current limit with increasing input voltage, preventing excessive overload output current. in this design the overload output current varies less than 2.5% across the entire input voltage range. controlling the current limit also reduces secondary component stress and leakage inductance spikes, allowing the use of a lower v rrm (30 v rather than 40 v) schottky output diode, d2. the primary side zener clamp vr1 ensures the peak drain voltage is kept below the 220 v bv dss rating of u1 under input surge and overvoltage events. during normal operation, vr1 does not conduct and c2 is suf? cient to limit the peak drain voltage. the primary bias winding provides control pin current after start-up. diode d3 recti? es the bias winding, while components r5 and c8 reduce high frequency switching noise and prevent peak charging of the bias voltage. capacitor c3 provides local decoupling of u1 and should be physically close to the control and source pins. energy storage for start-up and auto-restart timing is provided by c4. the secondary is recti? ed by d2 and the low esr tantalum output capacitors, c5-c7, minimizing switching ripple and maximizing ef? ciency. a small footprint secondary output choke l1 and ceramic output capacitor c9 are adequate to reduce high frequency noise and ripple to below 35 mv peak-peak under full load conditions. the output voltage is sensed by the voltage divider formed by resistors r8 and r9 and is fed to the low voltage 1.24 v reference u3. feedback compensation is provided by r6, r7 and c11 together with c4 and r4. capacitor c10 provides a soft-? nish characteristic, preventing output overshoot during start-up. low cost poe voip phone converter the basic circuitry to support ieee standard 802.3af power over ethernet (poe) is straightforward. class 0 signature and classi? cation circuits can be implemented with a single resistor and the required under-voltage lockout function is a voltage
rev. s 12/07 16 dpa422-426 www.powerint.com figure 27. poe interface circuit using a bipolar transistor pass-switch and dpa424p. u1 dpa424p d6 bav 19ws q22 si4804 d21 sl13 15 v q21 si4804 c2 1 f 100 v vr1 smaj 150 c5 47 f 10 v d41 bav19ws d31 20cjq060 r21 10 r22 10 r23 10 k vr21 c21 2.2 nf u2 t1 r1 649 k 1% r3 1.0 c22-c24 100 f 5 v vr41 6.8 v d42 in4148 c31 100 f 10 v c41 4.7 f, 35 v c25 1 f 10 v l1 1 h 2.5 a poe interface l2 16 h 4 a c6 4.7 f 20 v d11 bav19ws u3 lm431aim3 c11 2.2 f 10 v r14 1 k r15 10 k 1% r16 10 k 1% r4 160 r12 150 r13 11 c1 1 f 100 v u2 pc357 n1t r11 10 k pi-3824-040706 dpa-switch 5 v, 2.4 a rtn 7.5 v, 0.4 a 20 v, 10 ma c13 68 nf 4 5 3 6 7 18 72 7 8 6 5 43 ethernet (rj-45) connector r2 13.3 k 1% r52 20 k d101 dl4002 dl4002 d102 d103 dl4002 dl4002 d104 d105 dl4002 dl4002 d106 d107 dl4002 dl4002 d108 r22 10 k r23 174 k 1% r21 10 k r51 24.9 k 1% 1/4 w d51 bav19 d52 bav19 c51 1 nf 50 v r54 20 vr51 28 v (1,2) (4,5) (3,6) (7,8) d s c l f x control c12 100 nf r53 20 k q51 tip29c (100 v/1 a) or mmbta06 c4 220 nf q20 mmbts3906 controlled pass-switch. by adding this circuitry to the front end of a dpa converter, a low cost and low component count poe powered device (pd) power supply can be implemented. figure 27 shows a typical pd solution. the poe speci? cation requires the pd to provide three fundamental functions: discovery, classi? cation, and pass- switch connection. when input voltage is applied to the pd, it must present the correct discovery signature impedance in the voltage range of 2.5 vdc to 10 vdc. this impedance is provided by r51 in figure 27. the second classi? cation phase occurs at input voltages 15 vdc to 20 vdc. the pd must draw a speci? ed current to identify the device class (class 0 speci? es 0.5 ma to 4 ma). this is again accomplished by resistor r51. in the third phase, the bipolar pass-switch (q51 in figure 27) connects the input voltage to the power supply at voltages above approximately 30 vdc (28 v+vr52). zener diode vr51 conducts, driving the current through resistor r52 to the base of q51. resistor r53 prevents turn-on under other conditions. once the power supply has started, components d51, d52, c51 and r54 enhance the base-current drive by coupling power from the power supply bias winding. once the three start up phases have been successfully completed, the dpa-switch is allowed to function as a forward converter (described in figure 25 and accompanying text). key application considerations dpa-switch design considerations power table this section provides a description of the assumptions used to generate the power tables (tables 1 and 3 through 6) and explains how to use the information provided by them. all power tables: tables 1 and 3 through 6 maximum output power is limited by the device internal current limit. this is the peak output power which could become the continuous output power, provided adequate heat sinking is used. data assumes adequate heat sinking to keep the junction temperature at or below 100 c and worst case r ds(on) at t j = 100 c. the use of p and g packages are recommended for device dissipation equal to or less than 1.5 w only due to package thermal limitation. for device dissipation above 1.5 w, use r package. ? ? ?
rev. s 12/07 17 dpa422-426 www.powerint.com forward power tables: tables 1 (upper half), 3 and 4 output power ? gures are based on forward topology using schottky diode recti? cation. up to 5% higher output power is possible using synchronous recti? cation. dissipation data assumes a diode loss representing 6% of the total output power and combined loss in magnetic compo- nents representing 6% of the total output power. dpa-switch losses are based on a ratio between conduction and switching losses of approximately 3:1. these assump- tions are typical for a single 5 v output forward converter design using schottky recti? cation and adequately designed magnetic components. flyback power tables: tables 1 (lower half), 5 and 6 output power and dissipation ? gures are based on a 5 v output using schottky diode recti? cation with an ef? ciency of 85%. values are generated by calculation based on i 2 r ds(on) losses and characterization of switching losses, correlated to bench measurement of each dpa-switch device. device dissipations above 1.5 w are possible using the r package. however the forward converter topology is recommended for such higher power designs. the power tables provide two types of information. the ? rst is the expected device dissipation for a given output power. the second is the maximum power output. each table speci? es the input voltage range and assumes a single 5 v output using schottky diode recti? cation. for example, referring to table 1, for 36 vdc to 75 vdc input range, dpa424 would typically dissipate 1 w in a 23 w forward converter and has a maximum power capacity of 35 w. in the same converter, dpa425 would dissipate 0.5 w. selecting dpa425 with associated reduced dissipation would increase overall converter ef? ciency by approximately 2%. issues affecting dissipation: using synchronous recti? cation will tend to reduce device dissipation. designs with lower output voltages and higher currents will tend to increase the device dissipation listed in the power table. reduced input voltage decreases the available output power for the same device dissipation. tables 3 to 6 are the power tables for 16 vdc and 24 vdc input voltages. input voltages below 16 v are possible, but since the internal start-up current source is not speci? ed at voltages below 16 v, an external chip supply current should be fed into the control pin approximately equal to but less than i cd1 . dpa-switch selection use tables 1 and 3 through 6 to select the dpa-switch based on device dissipation. selecting the optimum dpa-switch depends upon required maximum output power, ef? ciency, heat sinking constraints and cost goals. with the option to externally reduce current limit, a larger dpa-switch may be used for lower power applications where higher ef? ciency is needed or minimal heat sinking is available. generally, selecting the next larger device, than is required for power delivery will give the highest ef? ciency. selecting even larger devices may ? ? ? ? 1. 2. 3. output power table 16-32 vdc range (forward) 2 total device dissipation product 3 0.5 w 1 w 2.5 w 4 w 6 w max power output 1 dpa422 3.5 w 4.5 w - - - 5.0 w dpa423 5 w 7 w - - - 7.5 w dpa424 7 w 10 w 15 w - - 15.5 w dpa425 10 w 14 w 22 w 27 w - 31 w dpa426 12 w 16.5 w 25 w 31 w 37 w 43 w table 3. output power table for 16-32 vdc input voltage. notes: 1. limited by device internal current limit. 2. see text in this section for a complete description of assumptions. 3. see part ordering information. output power table 16-32 vdc input range (flyback) 2 total device dissipation product 3 0.5 w 0.75 w 1 w 1.5 w max power output 1 dpa422 3 w - - - 4.5 w dpa423 5 w - - - 6 w dpa424 6.5 w 8.5 w 10 w - 11 w dpa425 7 w 10 w 12 w 15 w 22 w output power table 24-48 vdc range (forward) 2 total device dissipation product 3 0.5 w 1 w 2.5 w 4 w 6 w max power output 1 dpa422 5.5 w 7 w - - - 8 w dpa423 8 w 11 w - - - 11.5 w dpa424 11 w 16 w 23.5 w - - 25 w dpa425 16 w 22 w 35 w 43 w - 47 w dpa426 18 w 25 w 39 w 48 w 58 w 65 w table 4. output power table for 24-48 vdc input voltage (see table 3 for notes). table 5. flyback output power table for 16-32 vdc input voltage (see table 3 for notes). output power table 24-48 vdc input range (flyback) 2 total device dissipation product 3,4 0.5 w 0.75 w 1 w 1.5 w max power output 1 dpa422 3 w - - - 7 w dpa423 7 w - - - 8.5 w dpa424 8.5 w 11.5 w 14 w - 17 w table 6. flyback output power table for 24-48 vdc input voltage. notes: 1. maximum output power is limited by device internal current limit. 2. see text in this section for a complete description of assumptions. 3. see part ordering information. 4. higher switching losses may prevent dpa425 from delivering more power than a smaller device.
rev. s 12/07 18 dpa422-426 www.powerint.com give little or no improvement in ef? ciency due to the improvement in conduction losses being negated by larger device switching losses. figure 50 provides information on switching losses. this together with conduction loss calculations give an estimate of device dissipation. primary clamp a primary clamp network is recommended to keep the peak drain voltage due to primary leakage inductance to below the bv dss speci? cation. a zener diode combined with a small value capacitor connected across the primary winding is a low cost and low part count implementation. output recti? cation recti? cation of the secondary is typically performed using schottky diodes or synchronous recti? cation. schottky diodes are selected for peak inverse voltage, output current, forward drop and thermal conditions. synchronous recti? cation requires the additional complication of providing gate drive. the speci? ed line under-voltage and line overvoltage thresholds of dpa-switch simpli? es deriving gate drive directly from the transformer secondary winding for many applications. the turns ratio of the transformer together with the under/ overvoltage thresholds de? nes the minimum and maximum gate voltages, removing the need for zeners to clamp the gate voltage. soft-start generally a power supply experiences maximum stress at start- up before the feedback loop achieves regulation. for a period of 5 ms the on-chip soft-start linearly increases the duty cycle from zero to the default dc max at turn-on. in addition, the primary current limit increases from 85% to 100% over the same period. this causes the output voltage to rise in an orderly manner allowing time for the feedback loop to take control of the duty cycle. this integrated soft-start reduces the stress on the dpa-switch mosfet, clamp circuit and output diode(s), and helps prevent transformer saturation during start- up. also, soft-start limits the amount of output voltage overshoot, and in many applications eliminates the need for a soft-? nish capacitor. if necessary, to remove output overshoot, a soft-? nish capacitor may be added to the secondary reference. switching frequency the frequency pin of dpa-switch offers a switching frequency option of 400 khz or 300 khz. operating at 300 khz will increase the amount of magnetization energy stored in the transformer. this is ideal for applications using synchronous recti? cation driven directly from the transformer secondary where this energy can be used to drive the catch mosfet gate. transformer design it is recommended that the forward converter transformer be designed for maximum operating ? ux swing of 1500 gauss and a peak ? ux density of 3500 gauss. when operating at the maximum current limit of the selected dpa-switch (during overload conditions), neither magnetic component (transformer and output inductor) should be allowed to saturate. when a larger device than necessary has been selected, reducing the internal current limit close to the operating peak current limits overload power and minimizes the size of the secondary components. no-load and standby consumption cycle skipping operation at light or no load can signi? cantly reduce power loss. in addition this operating mode ensures that the output maintains regulation even without an external minimum load. however, if cycle skipping is undesirable in a particular application, it can be avoided by adding suf? cient pre-load. dpa-switch layout considerations the dpa-switch can operate with large drain current, the following guidelines should be carefully followed. primary side connections the tab of dpa-switch r package is the intended return path for the high switching currents. therefore, the tab should be connected by wide, low impedance traces back to the input decoupling capacitor. the source pin should not be used to return the power currents; incorrect operation of the device may result. the source is only intended as a signal ground. the device tab (source) is the correct connection for high current with the r package. the control pin bypass capacitor should be located as close as possible to the source and control pins and its source connection trace should not be shared by the main mosfet switching currents. all source pin referenced components connected to the line-sense or external current limit pins should also be located closely between their respective pin and source. once again, the source connection trace of these components should not be shared by the main mosfet switching currents. it is critical that the tab (source) power switching currents are returned to the input capacitor through a separate trace that is not shared by the components connected to control, line-sense or external current limit pins. any traces to the l or x pins should be kept as short as possible and away from the drain trace to prevent noise coupling. line-sense resistor (r1 in figure 25) should be located close to the l pin to minimize the trace length on the l pin side. in addition to the control pin capacitor (c6 in figure 25), a high frequency bypass capacitor in parallel is recommended as close as possible between source and control pins for better noise immunity. the feedback optocoupler output should also be located close to the control and source pins of dpa-switch. heat sinking to maximize heat sinking of the dpa-switch r or g package and the other power components, special thermally conductive pc board material (aluminum clad pc board) is recommended. this has an aluminum sheet bonded to the pc board during the manufacturing process to provide heat sinking directly and allow the attachment of an external heat sink. if normal pc board material is used (such as fr4), providing copper areas on
rev. s 12/07 19 dpa422-426 www.powerint.com both sides of the board and using thicker copper will improve heat sinking. if an aluminum clad board is used then shielding of switching nodes is recommended. this consists of an area of copper placed directly underneath switching nodes such as the drain node, and output diode to provide an electrostatic shield to prevent coupling to the aluminum substrate. these areas are connected to input negative in the case of the primary and output return for secondary. this reduces the amount of capacitive coupling into the insulated aluminum substrate that can then appear on the output as ripple and high frequency noise. quick design checklist as with any power supply design, all dpa-switch designs should be veri? ed on the bench to make sure that component speci? cations limits are not exceeded under worst case conditions. the following minimum set of tests for dpa-switch forward converters is strongly recommended: maximum drain voltage C verify that peak v ds does not exceed minimum bv dss at highest input voltage and maxi- mum overload output power. it is normal, however, to have additional margin of approximately 25 v below bv dss to allow for other power supply component unit-to-unit variations. maximum overload output power occurs when the output is loaded to a level just before the power supply goes into auto- restart (loss of regulation). transformer reset margin C drain voltage should also be checked at highest input voltage with a severe load step (50-100%) to verify adequate transformer reset margin. this test shows the duty cycle at high input voltage, placing the most demand on the transformer reset circuit. 1. 2. maximum drain current C at maximum ambient temperature, maximum input voltage and maximum output load, verify drain current waveforms at start-up for any signs of trans- former or output inductor saturation and excessive leading edge current spikes. dpa-switch has a leading edge blanking time of 100 ns to prevent premature termination of the on cycle. verify that the leading edge current spike does not extend beyond the blanking period. thermal check C at maximum output power, minimum input voltage and maximum ambient temperature, verify that temperature speci? cations are not exceeded for the transformer, output diodes, output choke(s) and output capacitors. the dpa-switch is fully protected against over- temperature conditions by its thermal shutdown feature. it is recommended that suf? cient heat sinking is provided to keep the tab temperature at or below 115 c (r package), source pins at or below 100 c (p/g packages) under worst case continuous load conditions (at low input voltage, maximum ambient and full load). this provides adequate margin to minimum thermal shutdown temperature (130 c) to account for part-to-part r ds(on) variation. when monitoring device temperatures, note that the junction-to- case thermal resistance should be accounted for when estimating die temperature. design tools up-to-date information on design tools is available at the power integrations website: www.powerint.com. 3. 4.
rev. s 12/07 20 dpa422-426 www.powerint.com v v pi-2883-060602 solder side component side top view s l c x transformer - + v + - dc out maximize hatched copper area for optimum heat sinking v via between board layers v opto- coupler inductor (coupled) output diode d dpa-switch dc in pi-3805-012904 t r a n s f o r m e r opto- coupler + dc out dc in + - v v v v v v v v v v dpa-switch heatsink bottom diode heatsink - v v cl xf sds dpa-switch s top side pcb bottom side pcb (two sided printed circuit board) top view maximize hatched copper area for optimum heat sinking via between board layers v - figure 28. layout considerations for dpa-switch using r package. figure 29. layout considerations for dpa-switch using g package.
rev. s 12/07 21 dpa422-426 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 33 (unless otherwise speci? ed) min typ max units control functions switching frequency f osc t j = 25 c frequency pin connected to source 375 400 425 khz frequency pin connected to control 282 300 317 duty cycle (prior to cycle skipping) dc min 46% maximum duty cycle dc max i c = i cd1 v l = 0 v 71 75 79 % i l = 80 a 52 62 71 i l = 115 a 32 42 57 control current at start of cycle skipping i c(skip) t j = 25 c; f osc = 400 khz dpa422 6.3 8.0 ma dpa423 7.2 9.0 dpa424 8.2 10.0 dpa425 10.0 12.0 dpa426 11.5 14.0 external bias current i b t j = 25 c; f osc = 400 khz dpa422 1.8 2.5 3.1 ma dpa423 2 2.8 3.5 dpa424 2.5 3.5 4.4 dpa425 3.6 4.8 6.0 dpa426 4.4 5.7 7.1 absolute maximum ratings (1,5) drain voltage .....................................................-0.3 v to 220 v drain peak current: dpa422......................................1.31 a dpa423......................................1.75 a dpa424....................................... 3.5 a dpa425...........................................7 a dpa426....................................... 9.6 a control voltage ................................................ -0.3 v to 9 v control current .........................................................100 ma line sense pin voltage ...................................... -0.3 v to 9 v external current limit pin voltage ........ -0.3 v to 9 v frequency pin voltage ....................................... -0.3 v to 9 v storage temperature-65 c to 150 c operating junction temperature (2) .................... -40 c to 150 c lead temperature (3) ....................................................... 260 c notes: 1. all voltages referenced to source, t a = 25 c. 2. normally limited by internal circuitry. 3. 1/16 from case for 5 seconds. 4. maximum ratings speci? ed may be applied, one at a time, without causing permanent damage to the product. exposure to absolute maximum rating conditions for extended periods of time may affect product reliability. theraml impedance thermal impedance: p or g package: ( ja ) ........................... 70 c/w (1) ; 60 c/w (2) ( jc ) (3) ............................................11 c/w r package: ( ja ) .................................................40 c/w (4) ( ja ) .................................................30 c/w (5) ( jc ) (6) ................................................2 c/w notes: 1. soldered to 0.36 sq. in. (232 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 2. soldered to 1 sq. in. (645 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 3. measured on pin 7 (source) close to plastic interface. 4. soldered to 1 sq. in. (645 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 5. soldered to 3 sq. in. (1935 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 6. measured at the back surface of tab.
rev. s 12/07 22 dpa422-426 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 33 (unless otherwise speci? ed) min typ max units control functions (cont.) softstart time t soft t j = 25 c; dc min to dc max 5 7.2 ms pwm gain dc reg t j = 25 c; i c = i c(skip) + i b )/2 -28 -22 -18 %/ma pwm gain temperature drift see note a -0.01 %/ma/c dynamic impedance z c t j = 25 c; i c = i c(skip) + i b )/2 10 15 22 dynamic impedance temperature drift 0.18 %/c control pin internal filter pole 30 khz shutdown/auto-restart control pin charging current i c(ch)) during startup and auto-restart: v c = 5.0 v; v d = 16 v & 40 v; t j = 25 c -5.2 -4 -3 ma average current at the beginning of softstart: v c = 5.0 v; v d = 16 v & 40 v; t j = 25 c -19 charging current temperature drift see note a -0.6 %/ c auto-restart upper threshold voltage v c(ar)u 5.8 v auto-restart lower threshold voltage v c(ar)l 4.5 4.8 5.1 v auto-restart hysteresis voltage v c(ar)hyst 0.8 1 v auto-restart duty cycle dc (ar) c control = 22 f; f osc = 400 khz; v x = 0 v 10 % auto-restart frequency f (ar) c control = 22 f; f osc = 400 khz; v x = 0 v 3.8 hz line-sense (l) and external current limit (x) inputs line undervoltage threshold current and hysteresis (l pin) i uv t j = 25 c threshold from off to on 48 50 52 a threshold from on to off 44.5 47 49.5 hysteresis 2 3 line overvoltage or remote on/off threshold current and hysteresis (l pin) i ov t j = 25 c threshold from on to off 135 149 a threshold from off to on 117 131 hysteresis 4 remote on/off negative threshold current and hysteresis (x pin) i rem t j = 25 c threshold from on to off -27 -21.5 -16 a threshold from off to on -25.5 hysteresis 4.5
rev. s 12/07 23 dpa422-426 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 33 (unless otherwise speci? ed) min typ max units line-sense (l) and external current limit (x) inputs (cont.) l pin short circuit current i l(sc) v l = v c 175 240 380 a v l = 0 v -230 -170 x pin short circuit current i x(sc) v x = 0 v normal mode -270 -230 -185 a remote off using l pin -105 -85 -65 line pin voltage (positive current) vl i l = i uv 2.05 2.35 2.6 v i l = i ov 2.1 2.5 2.9 x pin voltage (negative current) vx i x = -50 a 1.35 i x = -150 a 1.25 maximum duty cycle reduction onset threshold current il(dc) t j = 25 c 55 a remote off drain supply current id(rmt) v d = 40 v v x = 0 v v l = floating 0.6 1.1 ma v l = v c 0.9 1.5 l pin voltage turn-on threshold in synchronous mode v l(th) 0.6 1 1.4 v on-time pulse width for synchronization ton(sync) f osc = 400 khz 120 2250 ns f osc = 300 khz 120 3080 off-time pulse width for synchronization t off(sync) 0.25 7.7 s synchronous turn-on delay t delay(sync) from synchronous on to drain turn-on 250 ns frequency (f) input frequency pin threshold voltage v f 1.1 4 v frequency pin input current i f v f = 0 v -0.38 a v f = v c 17 120 frequency pin delay time t delay(vf) 2 s circuit protection self protection current limit (see note b) i limit t j = 25 c dpa422 di/dt = 225 ma/ s 0.86 0.935 1.0 a dpa423 di/dt = 300 ma/ s 1.16 1.25 1.34 dpa424 di/dt = 600 ma/ s 2.32 2.50 2.68 dpa425 di/dt = 1.25 a/ s 4.65 5.00 5.35 dpa426 di/dt = 1.75 a/ s 6.50 7.00 7.50
rev. s 12/07 24 dpa422-426 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 33 (unless otherwise speci? ed) min typ max units circuit protection (cont.) initial current limit i init v d = 35 v 0.9 a leading edge blanking time t leb t j = 25 c 100 ns current limit delay t il(d) i c = (i c(skip) + i b )/2 100 ns thermal shutdown temperature t j(sd) 130 137 145 c thermal shutdown hysteresis t j(sd)hyst 27 c power-up reset threshold voltage v c(reset) 1.5 2.75 4 v output on-state resistance r ds(on) dpa422 i d = 150 ma t j = 25 c 2.60 3.00 t j = 100 c 4.00 4.60 dpa423 i d = 300 ma t j = 25 c 1.30 1.50 t j = 100 c 2.00 2.30 dpa424 i d = 600 ma t j = 25 c 0.65 0.75 t j = 100 c 1.00 1.15 dpa425 i d = 1.25 a t j = 25 c 0.33 0.38 t j = 100 c 0.50 0.58 dpa426 i d = 1.75 a t j = 25 c 0.24 0.28 t j = 100 c 0.37 0.43 off-state drain leakage current i dss v x , v l = floating; v d = 150 v; t j = 125 c; i c = (i c(skip) + i b )/2 dpa422 33 a dpa423 65 dpa424 130 dpa425 260 dpa426 360 breakdown voltage b vdss v x , v l = floating; t j = 25 c; i c = (i c(skip) + i b )/2; see note c 220 v rise time t r measured in a typical application 10 ns fall time t f measured in a typical application 10 ns
rev. s 12/07 25 dpa422-426 www.powerint.com parameter symbol conditions source = 0 v; t j = -40 to 125 c see figure 33 (unless otherwise speci? ed) min typ max units supply voltage characteristics drain supply voltage see note d 16 v shunt regulator voltage v c(shunt) i c = (i c(skip) + i b )/2; t j = 25 c 5.6 5.85 6.0 v shunt regulator temperature drift i c = (i c(skip) + i b )/2 50 ppm/c control supply/ discharge current i cd1 output mosfet enabled v l = 0 v; f osc = 400 khz dpa422 1.6 2.0 2.4 ma dpa423 1.9 2.3 2.7 dpa424 2.6 3.0 3.4 dpa425 3.7 4.3 4.8 dpa426 4.8 5.4 6 i cd2 output mosfet disabled v l = 0 v; f osc = 400 khz 0.4 0.73 1.2 notes: for speci? cations with negative values, a negative temperature coef? cient corresponds to an increase in magnitude with increa s- ing temperature, and a positive temperature coef? cient corresponds to a decrease in magnitude with increasing temperature. for externally adjusted current limit values, please refer to figure 35 (current limit vs. external current limit resistance) i n the typical performance characteristics section. breakdown voltage may be checked against minimum bv dss speci? cation by ramping the drain pin voltage up to but not exceeding minimum bv dss . it is possible to start up and operate dpa-switch at drain voltages well below 16 v. however, the control pin charging current is reduced, which affects start-up time, auto-restart frequency, and auto-restart duty cycle. refer to figure 45, the characteristic graph on control pin charge current (i c ) vs. drain voltage for low voltage operation characteristics. a. b. c. d.
rev. s 12/07 26 dpa422-426 www.powerint.com pi-2039-033001 drain voltage hv 0 v 90% 10% 90% t 2 t 1 d = t 1 t 2 120 100 80 40 20 60 0 0246810 control pin voltage (v) control pin current (ma) 1 slope dynamic impedance = pi-2880-060302 figure 30. duty cycle measurement. 1.4 1.2 1 0.6 0.2 0.4 0.8 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 time ( s) drain current (normalized) pi-2889-061302 t leb (blanking time) + t il(d) (current limit delay) temperature range: -40 c to 125 c figure 32. typical drain operation current envelope. pi-2860-050602 5-50 v s4 40 v 0-15 v 0.1 f 47 f 470 5 w 470 0-200 k 0-70 k note: this test circuit is not applicable for current limit or output characteristic measurements. d s fx c l c control dpa-switch s2 s1 s3 figure 33. dpa-switch general test circuit. figure 31. control pin i-v characteristic.
rev. s 12/07 27 dpa422-426 www.powerint.com the following precautions should be followed when testing dpa-switch by itself outside of a power supply. the schematic shown in figure 33 is suggested for laboratory testing of dpa-switch. when the drain pin supply is turned on, the part will be in the auto-restart mode. the control pin voltage will be oscillating at a low frequency between 4.8 v and 5.8 v and the drain is turned on every eighth cycle of the control pin oscillation. if the control pin power supply is turned on while in this auto-restart mode, there is only a 12.5% chance that the control pin oscillation will be in the correct state (drain active state) so that the continuous drain voltage waveform may be observed. it is recommended that the v c power supply be turned on ? rst and the drain pin power supply second if continuous drain voltage waveforms are to be observed. the 12.5% chance of being in the correct state is due to the divide-by-8 counter. temporarily shorting the control pin to the source pin will reset dpa-switch, which then will come up in the correct state. bench test precautions for evaluation of electrical characteristics typical performance characteristics 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 1.0 -230 -180 -130 -80 -30 i x ( a) current limit (normalized to internal current limit) 0 pi-2838-032202 figure 34. current limit vs. external current limit pin current. 0.3 0.2 0.1 0.5 0.4 0.6 0.7 0.8 0.9 1.0 1.1 0 5 10 15 20 25 30 35 external current limit resistor r il (k ) current limit (normalized to internal current limit) pi-2839-032202 minimum typical maximum figure 35. current limit vs. external current limit resistance.
rev. s 12/07 28 dpa422-426 www.powerint.com 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-2872-051602 current limit (normalized to 25 c) 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-2865-051702 overvoltage threshold (normalized to 25 c) figure 38. external current limit vs. temperature with r il = 12 k . figure 39. overvoltage threshold vs. temperature. 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-2867-051502 under-voltage threshold (normalized to 25 c) 7.0 4.0 6.0 5.0 0.0 -200 -100 -50 -150 0 50 100 150 200 250 line-sense pin current ( a) line-sense pin voltage (v) pi-2871-051502 2.0 1.0 3.0 figure 40. under-voltage threshold vs. temperature. figure 41. line-sense pin voltage vs. current. 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-2868-051502 output frequency (normalized to 25 c) figure 36. frequency vs. temperature. 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-2866-051702 current limit (normalized to 25 c) figure 37. internal current limit vs. temperature. typical performance characteristics (cont.)
rev. s 12/07 29 dpa422-426 www.powerint.com typical performance characteristics (cont.) 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-2863-011904 control pin current (normalized to 25 c) figure 43. control pin current at minimum duty cycle vs. temperature. 1.6 1.0 1.4 1.2 0 -225 -250 -150 -175 -200 -125 -50 -25 -100 -75 0 external current limit pin current ( a) external current limit pin voltage (v) pi-2869-051502 0.4 0.2 0.6 0.8 v x = 1.375 - ? i x ? x 843 k -200 a i x -25 a figure 42. external current limit pin voltage vs. current 5.0 3.5 3.0 4.0 4.5 0.0 0102030405060 drain voltage (v) control pin charging current (ma) pi-2841-051502 1.0 0.5 1.5 2.5 2.0 v c = 5 v figure 45. i c vs. drain voltage. 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) pi-2864-051702 onset threshold current (normalized to 25 c) figure 44. max. duty cycle reduction onset threshold current vs. temperature. 1.1 1.0 0.9 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) breakdown voltage (normalized to 25 c) pi-176b-033001 figure 47. breakdown voltage vs. temperature. 1.2 0.8 1.0 0 -50 -20 0 25 50 75 100 125 150 junction temperature ( c) remote off drain supply current (normalized to 25 c) pi-2870-051502 0.2 0.4 0.6 figure 46. remote off drain supply current vs. temperature.
rev. s 12/07 30 dpa422-426 www.powerint.com part ordering information ? dpa-switch product family ? series number ? package identi? er g plastic surface mount dip (422, 423, 424 & 425 only) p plastic dip r plastic to-263-7c (available only with tl option) ? lead finish blank standard (sn pb) n pure matte tin (pb-free) (p & g) ? tape & reel and other options blank standard con? gurations tl tape & reel, (g package: 1000 min./mult., r package: 750 min./mult.) typical performance characteristics (cont.) 20 16 18 14 12 10 8 6 4 2 0 01 2345 drain voltage (v) pi-2849-050302 drain current (a) scaling factors: dpa423 = 0.18 dpa424 = 0.36 dpa425 = 0.72 dpa426 = 1.00 t case = 25 c t case = 100 c figure 48. output characteristics. 2.5 2 1.5 1 0.5 0 -50 -25 0 25 75 50 100 125 150 temperature ( c) pi-2850-011904 on-resistance (normalized to 25 c) figure 49. on-resistance vs. temperature. 0 20 40 60 80 100 120 140 160 10 100 1000 10000 pi-2851-011904 drain voltage (v) capacitance (pf) scaling factors: dpa423 = 0.18 dpa424 = 0.36 dpa425 = 0.72 dpa426 = 1.00 figure 50. c oss vs. drain voltage. 2.5 2 1.5 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 in-circuit peak drain current normalized to nominal device internal current limit pi-2877-061704 switching loss (w) at 400 khz scaling factors: dpa423 = 0.08 dpa424 = 0.20 dpa425 = 0.55 dpa426 = 1.00 data taken from a typical forward converter design. figure 51. typical switching loss. dpa 423 g n - tl
rev. s 12/07 31 dpa422-426 www.powerint.com pi-2076-101102 1 a k j1 4 l g 85 c n dip-8 d s .004 (.10) j2 -e- -d- b -f- dim a b c g h j1 j2 k l m n p q inches 0.367-0.387 0.240-0.260 0.125-0.145 0.015-0.040 0.120-0.140 0.057-0.068 0.014-0.022 0.008-0.015 0.100 bsc 0.030 (min) 0.300-0.320 0.300-0.390 0.300 bsc mm 9.32-9.83 6.10-6.60 3.18-3.68 0.38-1.02 3.05-3.56 1.45-1.73 0.36-0.56 0.20-0.38 2.54 bsc 0.76 (min) 7.62-8.13 7.62-9.91 7.62 bsc notes: 1. package dimensions conform to jedec specification ms-001-ab for standard dual in-line (dip) package .300 inch row spacing (plastic) 8 leads (issue b, 7/85). 2. controlling dimensions are inches. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 4. d, e and f are reference datums on the molded body. h m p q p08a pi-2077-041003 1 a j1 4 l 85 c g08a smd-8 d s .004 (.10) j2 e s .010 (.25) -e- -d- b -f- m j3 dim a b c g h j1 j2 j3 j4 k l m p a inches 0.367-0.387 0.240-0.260 0.125-0.145 0.004-0.012 0.036-0.044 0.057-0.068 0.048-0.053 0.032-0.037 0.007-0.011 0.010-0.012 0.100 bsc 0.030 (min) 0.372-0.388 0-8 mm 9.32-9.83 6.10-6.60 3.18-3.68 0.10-0.30 0.91-1.12 1.45-1.73 1.22-1.35 0.81-0.94 0.18-0.28 0.25-0.30 2.54 bsc 0.76 (min) 9.45-9.86 0-8 notes: 1. package dimensions conform to jedec specification ms-001-ab (issue b, 7/85) except for lead shape and size. 2. controlling dimensions are inches. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 4. d, e and f are reference datums on the molded body. k g a h .004 (.10) j4 p .010 (.25) m a s .420 .046 .060 .060 .046 .080 pin 1 .086 .186 .286 solder pad dimensions
rev. s 12/07 32 dpa422-426 www.powerint.com .165 (4.19) .185 (4.70) r07c to-263-7c pi-2664-122004 -a- ld #1 .580 (14.73) .620 (15.75) .390 (9.91) .420 (10.67) .326 (8.28) .336 (8.53) .055 (1.40) .066 (1.68) .100 (2.54) ref 0.68 (1.73) min .208 (5.28) ref. .024 (0.61) .034 (0.86) .225 (5.72) min .245 (6.22) min .000 (0.00) .010 (0.25) .010 (0.25) .090 (2.29) .110 (2.79) .012 (0.30) .024 (0.61) 8 - 0 .045 (1.14) .055 (1.40) .050 (1.27) notes: 1. package outline exclusive of mold flash & metal burr. 2. package outline inclusive of plating thickness. 3. foot length measured at intercept point between datum a lead surface. 4. controlling dimensions are in inches. millimeter dimensions are shown in parentheses. 5. minimum metal to metal spacing at the package body for the omitted pin locations is .068 in. (1.73 mm). .004 (0.10) .315 (8.00) .128 (3.25) .038 (0.97) .050 (1.27) .380 (9.65) .638 (16.21) solder pad dimensions
rev. s 12/07 33 dpa422-426 www.powerint.com notes
rev. s 12/07 34 dpa422-426 www.powerint.com notes
rev. s 12/07 35 dpa422-426 www.powerint.com revision notes date f final release data sheet. 6/02 g updated figure 25 and text description. 9/02 h corrected missing text on page 9 and corrected table 4. updated r package description. revised thermal impedances (q ja ), dc min , v f , i f , and bv dss . updated figure 25 and description in text. 4/03 i corrected text errors on pp. 1, 7 and 20. 5/03 j figure 25 and description in text updated. 5/03 k added p and g packages. 1/04 l corrected figure 3. 4/04 m added package information to table 1. revised figure 13. added lead-free ordering information. 12/04 n minor error corrections. 2/05 o added s-pak. 7/05 p added notes to table 6. 7/05 q updated figure 27 to best re? ect current requirements for poe. 5/06 r added dpa422. 2/07 s removed s-pack. 12/07
for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integra tions. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a licens e under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in s igni? cant injury or death to the user. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, dpa-switch, peakswitch, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2007, power integrations, inc. 1. 2. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) rm 807-808a pacheer commercial centre, 555 nanjing rd. west shanghai, p.r.c. 200041 phone: +86-21-6215-5548 fax: +86-21-6215-2468 e-mail: chinasales@powerint.com china (shenzhen) rm a, b & c 4th floor, block c, electronics science and technology bldg. 2070 shennan zhong rd. shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via de amicis 2 20091 bresso mi italy phone: +39-028-928-6000 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg., 2-12-11 s hin-yokohama, kohoku-ku, yokohama-shi, kanagawa 222-0033 phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #15-08/10 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-140 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760

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